1. Field of the Invention
The present invention generally relates to a processor and a synchronous data transfer system using the processor, for high-speed data transfer between a memory and a peripheral device in accordance with the direct memory access (hereinafter, referred to as DMA) system.
2. Description of the Related Art
In a synchronous system in which a processor and peripheral devices are connected to a memory via the same bus, data may be read by a peripheral device from the memory without being directed by the processor (CPU) such that the data is directly transferred between the peripheral device and the memory. Such a data transfer system is referred to as a DMA data transfer.
FIG. 1 shows a synchronous system according to the related art. A CPU 1, a DMA controller (hereinafter, referred to as DMAC) 2, a peripheral device 3 and a memory 4 are connected to a data/address bus 10. When the DMA transfer is performed, the peripheral device 3 outputs a DMA request signal a to the DMAC 2. When the DMA request signal a is input to the DMAC 2, the DMAC 2 outputs a data bus use request signal b to an arbiter 5 in order to acquire a right to use the bus 10 from the CPU 1. When the data bus use request signal b is input to the arbiter 5, the arbiter 5 outputs a signal c for suspending the use of the bus 10 to the CPU 1. When the signal c is input to the CPU 1, the CPU 1 grants the right to use the bus 10 to the arbiter 5 and notifies the arbiter 5 accordingly by outputting a predetermined response signal d (referred to as a bus acknowledge signal in some cases) to the arbiter 5. The arbiter 5 receiving the predetermined response signal d outputs a signal e for enabling the use of the bus 10 to the DMAC 2. The DMAC 2 receiving the signal e outputs a DMA transfer enable signal f to the peripheral device 3 so as to execute DMA transfer between the peripheral device 3 and the memory 4.
As described above, in the system according to the related art, the right to use the bus 10 is granted to the peripheral device 3 immediately upon the input of the DMA request signal a from the peripheral device 3 so that the DMA transfer between the peripheral device 3 and the memory 4 is immediately enabled, irrespective of whether the CPU 1 is using the bus 10.
In the following description, it is assumed that instructions supplied to the CPU 1 demand that a cycle in which the CPU 1 uses the data/address bus 10 (hereinafter, referred to as a CPU cycle) and an idle or sleep cycle (hereinafter, referred to as an idle cycle) alternate.
FIG. 2 is a time chart showing a bus cycle occurring when the DMA request signal a is output by the peripheral device 3. As described already, the system according to the related art is constructed such that the DMAC 2 grants the right to use the bus 10 to the peripheral device 3 immediately upon the input of the DMA request signal a from the peripheral device 3 to the DMAC 2. When a series of DMA request signals arrive from the peripheral device 3 in three consecutive cycles, the right to use the bus 10 is immediately granted to the peripheral device 3. After performing the DMA transfer for three cycles, the CPU 1 is granted the right to use the bus 10 so that the CPU cycle 1, the idle cycle and the CPU cycle 2 are performed in the stated order.
When the peripheral device 3 issues a DMA request while the CPU 1 is using the bus 10, the process by the CPU 1 is suspended, reducing the processing performance of the CPU 1.
Various types of DMAC are proposed in order to resolve the aforementioned problem. Japanese Laid-Open Patent Application No. 4-49457 discloses a DMAC whereby a data transfer execution cycle subsequent to acquisition of the right to use the bus is controlled in accordance with the status of use of the bus. More specifically, when valid DMA request signals are received from peripheral devices, an order of priority is assigned to each of the request signals. The DMA transfer is started in a channel assigned the highest order of priority. Only one of a predetermined number of bus cycles is used for DMA transfer. When an access from the CPU occurs while the bus is used in the DMA transfer, an interval of one bus cycle is introduced before a signal for permitting the DMA transfer is output to the DMAC. With this arrangement, the CPU processing while the DMA transfer is being executed is improved. However, the DMAC according to Japanese Laid-Open Patent Application No. 4-49457 grants the right to access the bus to a peripheral device immediately when a high-priority request for using the bus is issued by the peripheral device, even when the CPU is using the bus. Accordingly, the process by the CPU may have to be suspended, thus causing the processing performance of the CPU to suffer.
Japanese Laid-Open Patent Application No. 4-116751 discloses a data transfer system in which the time in which the bus is occupied by DMA transfer is reduced so that the time in which the CPU is caused to sleep is reduced. However, the system according to Japanese Laid-Open Patent Application No. 4-116751 also grants the right to use the bus to a peripheral device immediately when the peripheral device requests the use of the bus, irrespective of how the bus is accessed by the CPU. Accordingly, the process by the CPU may have to be suspended, thus causing the processing performance of the CPU to suffer.
Japanese Laid-Open Patent Application 8-106432 discloses a DMA control circuit in which two data buses, one for the access by the CPU and the other for DMA transfer, are provided so that the CPU process need not be suspended even when the DMA transfer is proceeding. While such a DMA control circuit prevents the CPU processing performance from suffering due to the DMA transfer, the cost of the resultant data transfer system is high due to the provision of the two buses.
Japanese Laid-Open Patent Application 5-204826 discloses a data processing device in which a DMA request signal directly input from the DMAC to the CPU is handled in an identical manner as a bus access request signal generated inside the CPU such that both the DMA request signal and the bus access request signal are handled as a prerequisite to generate a bus cycle. According to such an arrangement, a non-used period elapsed between an output of a hold response signal from the CPU in response to a DMA request and the DMA transfer is eliminated, and a non-used period elapsed between the completion of the DMA transfer and the subsequent use of the data bus by the CPU is eliminated. According to this data processing device, the non-used period in which the data bus is not used is reduced. However, the right to use the bus is granted to a peripheral device immediately upon a request therefrom for using the bus, irrespective of how the CPU accesses the bus. Accordingly, the process by the CPU may have to be suspended, thus causing the processing performance of the CPU to suffer.